Flash memories are Electrically Erasable Programmable Read-Only Memory (EEPROM) memories that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed. All memory cells in the erase block are erased in a single operation.
Error corrective code requirements for NAND flash memories are increasing as flash memory geometries shrink and the size of each cell is reduced. Next generation NAND flash memories have lower endurance and higher ECC requirements. For example 16 nm NAND flash from one manufacturer might need 40 bits of ECC to achieve 3 k program erase cycles. This is much lower endurance and a much higher ECC requirement than prior generations of NAND flash. At the same time, the endurance requirements of applications have not changed. To meet market needs, a system level approach towards endurance management needs to be taken. There is a direct correlation between the ECC level that a controller can implement and the number of program erase (PE) cycles that a NAND flash can be used for reliably.
Meeting the ECC and endurance requirements within limited resources of Field Programmable Gate Arrays (FPGAs) requires careful system design. Further, additional NAND flash memory requirements include reducing the overall power of the ECC subsystem, which, in some instances, can account for over 80% of the logic on a high performance NAND flash controller.